This invention relates generally to field programmable gate array (“FPGA”) integrated circuit devices, such as programmable logic devices (“PLDs”), and more particularly to interface circuitry for configuring an embedded hard IP block in a FPGA device and related operating methods for such circuitry.
FPGAs are well-known devices as shown, for example, by such references as Cliff et al. U.S. Pat. No. 5,689,195, Cliff et al. U.S. Pat. No. 5,909,126, Jefferson et al. U.S. Pat. No. 6,215,326, and Ngai et al. U.S. Pat. No. 6,407,576. In general, an FPGA is a general-purpose integrated circuit device that is programmable to perform any of a wide range of logic tasks. FPGA technology is well-known for its ability to allow one common hardware design to be programmed to meet the needs of many different applications. Rather than having to design and build separate logic circuits for performing different logic tasks, general-purpose FPGAs can be programmed in various different ways to perform those various logic tasks. Many manufacturers of electronic circuitry and systems find FPGAs to be an advantageous way to provide system components because they can be manufactured in large quantities at low cost.
To facilitate the use of programmable logic resources in certain applications, hard intellectual property (“hard IP”) blocks, or design blocks represented as mask layouts, may be coupled to programmable logic resource core circuitry. Data from circuitry external is typically sent to a programmable logic resource through a particular pin and to a corresponding I/O port where the data is decoded and sent to a corresponding data port in the IP block for processing. Similarly, data from the IP block is typically sent to circuitry external to the package through a data port to a corresponding I/O port where the data is encoded and sent to a corresponding pin for output.
The performance of FPGA architectures has increased remarkably in recent years due, in part, to reuse at the layout level of hard IP blocks. Advantages of hard IP reuse are numerous, including the ability to optimize the hard IP directly at the layout level, which enables faster design. Hard IP reuse can also accelerate a product's time to market by migrating a cell library or a block from an old design into a new design.
FPGA integrated circuit devices with embedded hard IP blocks are now used in a multitude of high-speed applications, such as high-speed serial interfaces (“HSSIs”). These interfaces often process serial input data at rates in excess of several Gpbs. For example, Lee et al. U.S. Pat. No. 6,650,140, shows a PLD that includes HSSI circuitry that can support several high speed serial (“HSS”) standards.
To support increasing demands for dynamic, on-the-fly hard IP configuration, a separate configuration register bank is provided. Modeled after the MDIO (Management Data I/O) interface common in Ethernet standards, this new hard IP configuration interface is referred to as Dynamic Partial Reconfigurable I/O (“DPRIO”). Many hard IP control signal I/Os that can tolerate the latency of dynamic reconfiguration—after power-up and FPGA programming, but during normal functional mode—have been removed and are now controlled by DPRIO, thus saving valuable interface pins on the FPGA fabric side. Particularly for use with embedded hard IP devices that have a large number of configurations, it would be highly desirable to have an elegant, robust, and user-friendly DPRIO interface solution for dynamically reconfiguring embedded hard IP blocks.